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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit
ADDRESS MAP
DK101 Daughter Card address space begins at 0x81000000.
DK2000 Daughter Card address space begins at:
0x30000000 for slot 0
0x40000000 for slot 1
0x50000000 for slot 2
0x60000000 for slot 3
All offsets given below are relative to the beginning of the daughter card address space (shown above).
Table 1. Daughter Card Address Map
OFFSET
0X0000
to
0X0015
0X1000
to
0X10ff
0X2000
to
0X20ff
0X3000
to
0X30ff
0X4000
to
0X40ff
DEVICE
FPGA
T1/E1/J1
Transceiver #1
T1/E1/J1
Transceiver #2
T1/E1/J1
Transceiver #3
T1/E1/J1
Transceiver #4
DESCRIPTION
Board identification and clock/signal routing
DS21Q55 T1/E1/J1 transceiver, port 1
DS21Q55 T1/E1/J1 transceiver, port 2
DS21Q55 T1/E1/J1 transceiver, port 3
DS21Q55 T1/E1/J1 transceiver, port 4
Registers in the FPGA may be easily modified using the ChipView host-based user-interface software along with
the definition file named “DS21Q55DC_FPGA.def.”
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